CROSS CLOCK vhdl

Whats wrong with emptying a FIFO? if you have proper data flow control, and dont just expect valid data on every clock cycle (ie. you have a data_valid control signal) you shouldnt have a problem.

with video, you get about 80/20 valid data to blanking ratio, with the blanking region not valid. You get a long period of inactivity that is likely to empty your fifos.

What is the reason for not allowing fifos to get empty? I can understand the full problem (espcially if its video, you will lose syncronisation on the data) with pixels being dropped.