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Altera_Forum's avatar
Altera_Forum
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10 years ago

Critical warning in the PLL

Hello All,

I am struck up with one of the critical warning issue in the PLL.

Critical Warning (176598): PLL "pll:pllInst|altpll:altpll_component|pll_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_AJ16"

Can anyone please help me to fix this critical warning issue.

Regards,

Kishore Kumar K

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi Kishore,

    The PLLs inside the FPGA have specific input pins that should be used to properly compensate the output clocks. If you don't care about compensation, you could use the "No compensation mode" of the PLL and this warning will disappear.

    However, if compensation is necessary you need to choose the correct clock input pin to feed this PLL (this information can be found on the "Clock Networks and PLLs" documentation of the FPGA device family)

    Regards,

    Thiago