Forum Discussion

New Contributor

6 years ago

Critical Warning 16248 (pin is placed too close with ADC pins) and TSD use.

Hi, For my current project i use an IntelFPGA MAX10 (10M40DAF484) and i use a lot of the available IO's. Moreover, i need to use the internal temperature sensor. So i add the hard ADC IP and my own...

AnandRaj_S_Intel

Regular Contributor

6 years ago

Hi ,

Kindly find the below KDB for your reference. Maybe there is a chance of generation of noise by the GPIO pin, So better to follow the Quartus recommendation.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd03032016_970.html

Regards,

Anand

Forum Discussion

Critical Warning 16248 (pin is placed too close with ADC pins) and TSD use.

Recent Discussions

Unable to Generate Valid PAM4 Eye Diagram and BER Measurements on Stratix 10 SI E-Tile Native PHY

Agilex 5 D-Series HVIO IOPLL runtime reconfiguration: C0 write succeeds, but output remains 100 MHz

Cyclon 5 tampering protection bit

PCIe Simulation using Quartus Pro 25.1.1

Is VCCPD = 3.3V and VCCIO = 2.5V allowed on an Arria V?