Honored ContributorCyclone IV GX
How do create an external SRAM pin assignment? The SRAM is 512K x 8. The SRAM has - Address A[18:0] - Data DQ[7:0] - OE output - E chip enable - W write enable I know there is ALTMEMPHY megafunction, my understanding this for SDRAM and QDR II SRAM. should I use this also to create SRAM pin assignments? At this point I'm need pin assignments for board schematic and pdb build.
Honored Contributor1. First, create a mockup top level file with all the signals your FPGA will need: the SRAM signals you described, etc, etc.
2. Then compile the design and fire up the Pin Assignment Editor in order to assign the signals to actual FPGA pins and specify the I/O standard. Finaly, in order to make sure you have a viable pin assignment, do two things: a) read the pin assignment guidelines b) compile your design to see if there are no errors c) open the .pin file Quartus has produced and make sure the connections in your PCB match the contents of that file Never, ever, ever, sign of a PCB for manufacturing before at least doing these three steps!!! Rinse and repeat until you're happy. You'll proably will be changing the pin assignment as you design the PCB in order to make the routing easier. Some (most) EDA tools offer some support to help you with this.Honored ContributorFor an SRAM you are right that you shouldn't use the ALTMEMPHY function.
If you are using SOPC Builder/QSys, you should add a tristate bridge and create a component with a tristate avalon slave interface to add the SRAM to your system. If you aren't using SOPC Bulider or QSys then you'll have to write your own controller but it's very easy with an SRAM.Honored ContributorDaixiwen,
I've started the pin assignment backwards, noice mistake. Using pin planner to already assign some of the pins. To create top level design file, pin planner has two icons "set up" and "create". I'm hoping top level design file is the same as the header file (?) will see. If all works out will switch over and work through your process. Finding the pin assignment guidelines can be very tricky with lots of got-ya! Good design check .pin file vs schematic suggestion.Honored ContributorThe top level file is the "main" file for your design, whose I/O signals will be mapped to actual pins.
Eventually, you will be instantiating your SOPC within your top level file. I like to start by writing an empty top level file, which just lists the I/O signals so I can perform pin assign. But using the pin planner to assign pins and then have the pin planner create an empty top level file also works fine.
