First, I think I know why you don't get to choose the radix in SignalTap, looking at your list file output. You need to select all your DATA and group them. Then, you can choose a radix on the group. You can collapse the group so that only the bus/group value shows up. I am not next to computer to verify that.
Second, the sample index matches the tick value in the waveform viewer. 0 means the trigger position. negative value means the sample collected before trigger position. Each sample is collected upon posedge of your acquisition clock.
Third, I agree with the previous reply. You most likely have a real 50MHz clock. You should use it for reliability. That said, you have a simple setup. It can work with generated clock too. You just have to do a proper timing closure on that. It can get tricky. If you are new to FPGA, it can be too much of an adventure.
Forth, when you use 50MHz, you need to enable the storage qualifier feature. Choose "conditional", most likely. You need to define a condition that matches your 200K data output so that you'll only see the samples you care and filter out the idle data. I often add a counter as well to know how many clocks occurs between each sample, otherwise, there is just a dotted bar showing that two samples are not continuous. With that counter value, you can disable "record discontinuity" (something like that) so that your waveform is not cluttered by those dotted lines.
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