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Thanks for your reply; another question I have is that:
I implemented Sigma-Delta ADC on FPGA and my 8-bit digital output are @ 200 kS/s; However the input sampling frequency is 50MHz
when I want to capture my 8-bit output by SignalTap, in signal configuration part, I was asked to enter the clk; The question is which value for clk should i choose?200Ks/s or 50 MHz?
and when I captured the data the sample index start from -1024 to 7167 I wonder why it doesn't start from 0 to 8192? is it important? or I can consider the -1024 as first sample captured? the text file is as bellow
Signal Legend:
Key Signal Name
0 = DATA[0]
1 = DATA[1]
2 = DATA[2]
3 = DATA[3]
4 = DATA[4]
5 = DATA[5]
6 = DATA[6]
7 = DATA[7]
Data Table:
Signals-> 0 1 2 3 4 5 6 7
sample
-1024 1 1 0 0 0 1 0 0
-1023 1 1 0 0 0 1 0 0
-1022 1 1 0 0 0 1 0 0
-1021 1 1 0 0 0 1 0 0
-1020 1 1 0 0 0 1 0 0
. . . 7165 0 0 1 0 1 1 0 0
7166 0 0 1 0 1 1 0 0
7167 0 0 1 0 1 1 0 0
Thank you
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I wouldn't worry about sample indices as it depends on trigger setup.
If you have true 200KHz clock then use it otherwise you will have your values repeated many times on faster clock and you will need to pick up one sample from each repeated set.
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