Create NIOS system with SRAM

Hi.

I started to work with FPGA and Altera system about 2 month ago and as soon as I thought I start to understand something, I'm in dead end.....AGAIN! I think my problem is still that I don't know what the SoPC-Builder is creating automaticly and what I have to write in HDL by my self.

I try to add SRAM to my system. I use DE2-115 board. According to the datasheet it's the U17 block with total size of 2MB and datawidth of 16 bit. Best for my purpose would be SRAM with 8 bit datawidth and 2 MB toal size. In the SoPC builder I found IDT71V416 SDRAM controller. It's 16 bit width but it's ok to get started I guess. I add this one and a tristage bridge but then I have 32 bit datawidth in my generated system hdl file and some signals I just don't know to what connect them to. Also I have no hdl file like "sram_0.vhd" as i had by adding SDRAM controller, which works without any problem.

So my questions are: what do I have to do to use the SRAM chip on my FPGA? Do I have to write the controller itself or even some kind of instance of SRAM? Is datawidth of 8bit even possible? What do I have to do with SRAM_CE_N, SRAM_OE_N, SRAM_LB_N and SRAM_UB_N? There are no similar signals in my NIOS-System file automaticly created by SoPC-Builder. Am I on the right way or I'm doing something totaly wrong?

Maybe all this questions are stupid, but I'm realy frustrated, don't know what to do at this point. Some help would appreciate.

Thanks.