Honored Contributor
Honored ContributorAll right, thank you all.
--- Quote Start --- It is the same with Sopc Builder. The interconnection fabric will assert the read and write signals only on one slave, depending on the address you use. In order to find out what is going on with your system I recommend to use signaltap and monitor the signals simultaneously on your masters and your slaves, to see what is going on. --- Quote End --- That what I was expecting too. But, hell, I don't know what I'm doing wrong or maybe......I just don't know. As soon as I add a chipselect signal to my slave, eerything works and the modelsim simulation looks fine, without it my slave gets read/write signal every time my DMA performs it, no matter the address. Oh well, it works. One signal too much is fine by me as long as stuff works. Things could be better but they could be also much more sad and depressing :D Maybe someone had similar problem and knows what to do. Until than I'll just chipselect slaves. Regards, Vlad.
