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GD76
Occasional Contributor
Occasional Contributorcreate falling edge virtual clock
Trying to understand to concept of virtual clock. A virtual clock is created from external clock but think that is created at rising edge. Both are 20MHz. How to create a virtual clock from SYCLK but...
GD76Occasional Contributor
Occasional ContributorWhat I did that seem to solve the problem is : Take the 50ns clock invert at setup failing clock pins.
create_generated_clock -invert -source [get_ports {SYSCLK}] -name {DSACKCLK} [get_pins RAM_CONTROL:i13|q3|clk]
