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I've gone through the online training for timing quest, I've read everything I can find in the user manual, and I'm still missing something..
I really want to be able to use create_clock and create_generated_clock on a pre map net name. After mapping, the net names a all changed up (and with fine reason - optimization and all), and SDC files are not read until after mapping and before fitting....
It seems like there must be a way to do this more automatically without mapping first, running the gui, doing a bunch of searching, getting it wrong a bunch of times, retrying etc...
One idea I had was the try to keep the wire around, even though that certainly may be less optiimal with
wire generatedClockA /* synthesis keep = 1 */; // verilog
But this doesn't keep the net around, or at least I can't see that it does (hmm, can I dump out a dump map netlist to verify this or not ? Meaning that if I try to use that net in the create clock command, it doesn't find that net.
I guess the clock divider always sticks around, but it's buried down a few levels of hierarchy, as the report tells me *after* I've run fit...
I'm must be missing something basic here, or are clocks really always a completely interactive setup everytime you change add or delete internal clocks???
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Hi,
normally timing constraints are applied to a design before synthesis and mapping, because the constraint should guide the tool to reach the design requirements.
Why do you want to set the contraints on the pre-mapped netlist ?
Kind regards
GPK
Honored Contributor
