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DB's avatar
DB
Icon for New Contributor rankNew Contributor
6 years ago

CRC in Cyclone V Devices

Hi, I have got questions regarding the CRC capability of Cyclone V devices: The following document describes the behaviour on pages 291 - 301: https://www.intel.com/content/dam/www/programmable/us...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

1) What is the meaning of a "frame"? Does a Cyclone V device has one frame, or more? If more, where can I get the number of frames?

Each device will have a certain number of frame. We do not release the frame number but it will be within 16bit addressing for Cyclone V

2) It is described, that the error detection frequency (internal oszillator frequency) varies from 42.6 MHz to 100 MHz. Where is the error detection frequency of a device defined? Where can I get this information?

It is define in the Quartus setting.

If you look into the time used, Tmin using ms while Tmax is in second. That is the reason of using different calculation.