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CFree1's avatar
CFree1
Icon for New Contributor rankNew Contributor
7 years ago

CRC_ERROR pin I/O standards.

I wish to use configuration error detection IP to report corruption of the configuration image but I am not sure what I/O standards are available on the CRC_ERROR pin.

The 'device and pin options' of Quartus has a tick-box called "Enable open drain on CRC_ERROR pin". If this is not ticked, what output drive circuit can I expect? Will it actively drive the pin to VCCIO when an error occurs and pull it to GND when there is no error? And which I/O standard will this be? Also, what is the behaviour of the pin during configuration and during initialisation?

The handbook also talks about a "cycloneiv_crcblock" primitive atom. Does anyone know what a primitive atom is and how I can use it to access the CRC storage register to inject an error?

The device is Cyclone IV E. Quartus prime 18.0.

2 Replies

  • CFree1's avatar
    CFree1
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi, thanks for your great answer.

    Perhaps intel can clarify the use of that tick-box because I found a knowledge base entry (link below) which agrees with your answer and states that the box is greyed-out from Quartus10 onwards. Fair enough it, has had many versions since and they may have a reason to start using the box again but the fact it isn't greyed-out any more suggests to users that it has a function again.

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05262010_517.html

  • SAR's avatar
    SAR
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago
    1. The CRC_ERROR pin is always open drain regardless of this checkbox hence pulled up using external pull-up resistor.(state is high)
    2. During the configuration process, the CRC_ERROR pin is a regular I/O pin until the FPGA enters user mode and then will start to function as the CRC_ERROR pin.
    • Even though the I/O pins are tri-stated during the configuration process, this I/O (CRC_ERROR) pin buffer is turned off and is connected to an external 10k ohm pull-up, this will cause the I/O (CRC_ERROR) pin to be pulled high.(CRC_ERROR pin is high during configuration)
    • the CRC_ERROR pin will begin to drive low once the device enters usermode. If you have the optional INIT_DONE pin enabled then the CRC_ERROR pin will be driven low once INIT_DONE is released.
    • When the FPGA enters user mode, the I/O (CRC_ERROR) pin buffer is turned on and will function as the CRC_ERROR pin where it will stay low until an error is detected.

    For voltage level check the voh voltage based on I/O Standard or VCCIO of bank 6.

    page 458 for I/O STD: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf

    CRC error detection is only supported in Cyclone IV E devices with VCCINT 1.2 V, and not in Cyclone IV E devices with VCCINT 1.0 V.