- The CRC_ERROR pin is always open drain regardless of this checkbox hence pulled up using external pull-up resistor.(state is high)
- During the configuration process, the CRC_ERROR pin is a regular I/O pin until the FPGA enters user mode and then will start to function as the CRC_ERROR pin.
- Even though the I/O pins are tri-stated during the configuration process, this I/O (CRC_ERROR) pin buffer is turned off and is connected to an external 10k ohm pull-up, this will cause the I/O (CRC_ERROR) pin to be pulled high.(CRC_ERROR pin is high during configuration)
- the CRC_ERROR pin will begin to drive low once the device enters usermode. If you have the optional INIT_DONE pin enabled then the CRC_ERROR pin will be driven low once INIT_DONE is released.
- When the FPGA enters user mode, the I/O (CRC_ERROR) pin buffer is turned on and will function as the CRC_ERROR pin where it will stay low until an error is detected.
For voltage level check the voh voltage based on I/O Standard or VCCIO of bank 6.
page 458 for I/O STD: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf
CRC error detection is only supported in Cyclone IV E devices with VCCINT 1.2 V, and not in Cyclone IV E devices with VCCINT 1.0 V.
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