Forum Discussion
Honored ContributorCPRI on stratix IV GT board
I'm trying to use CPRI IP core on a stratix IV GT board.Actually the supported device familys from the user guide do not include stratix IV GT. However, the similar stratix IV GX is included. but when I set the project device as stratix IV GT, I can generate CPRI core. Then I tried to set the project device as Max10, which absolutely does not support this IP core,I can't generate as I expected. The only problem is that I can't simulate my design under GT. So I only verified simulatoin under GX. When I tested my design on real board, I found that although the Interface response signal "waitrequeset" is functional, the CPRI CPU interface can not be read or written.And other CPRI functions like reset, 8b/10b ,RX status display are right. Now I just want to know whether the cpri core supports stratix iv gt.
One kind of warning that may matters is : "Synthesized away the following RAM node"…… note that I got almost the same warning,and exact the same critical warning when I set the device as GX during compilation. Here I attach the warnings during the compiling. Thanks in advance!12 Replies
Altera_ForumThats great news. please send me at [email protected].
I have also some other designs on 10G-EPON, I was thinking to finally test them and upload here. Thanks a lot.- Altera_Forum
I'm glad to tell you that he allows me to give you the design. So, should I mail you the project? What's your E-mail address?
- Altera_Forum
Dear Sam Lee,
Thank for your reply, Yeah, fine. Once you have please share with me. I was trying to test the design coming days with REC loop back. Thanks a lot. - Altera_Forum
Well,I'm sorry that I must ask my advisor for permission,he doesn't reply me yet. I'll let you know as soon as he replys. As for the critical warnings, I did not take it seriously. Whether I set the device as GX or GT, or included nothing but IP core in my design, this critical warning came out anyway, so I think it doesn't matter. You may do some experiments.
- Altera_Forum
Dear Sam Lee,
That is really interesting to me. If you already have communication between two IP cores. Is it possible to get that design? I should solve those problems. I received CPRI (OpenCL) license from Altera, I will try to configure ALTGX_RECONFIG in top module to check still I get critical warring that you specified. Thanks a lot. - Altera_Forum
I simulated both REC/RE loopback and basic communication between REC and RE. I achieved communication between two IP cores but leave some mistakes unsolved, since I decided to change platform at that point. Wish this could help you.
- Altera_Forum
Dear Sam Lee,
Thank you for your reply, As per CPRI specification, I was trying to make communication between REC and RE in single design to check in Simulation. Did you also make communication between REC and RE, or only with REC/RE loopback testing. We ordered netFPGA SUME boards, still waiting for them. Thanks a lot. - Altera_Forum
My simulation on GT is totally fine, but it turned out that the design can not work on real board. I carefully reviewed my design and I don't think there is any mistake. FYI, I'm already using Xilinx platform.I'm sorry that you should find another board,otherwise you may waste time.
- Altera_Forum
Dear Sam Lee,
Thank you for your reply. I can see from the below link in IP cores. They did not specified about Stratix IV GT. Did you able to simulate the design at least? As of know we have only Stratix IV GT boards. Thanks a lot. - Altera_Forum
Please check my reply above, I only got reply from Altera technical documentation team, they said that "the IP core provides Stratix IV device family support only for Stratix IV GX devices", which means GT is not gonna work. I recommand you to choose other device family or use Xilinx platform.
