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Altera_Forum's avatar
Altera_Forum
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15 years ago

CPLD input pin disabling using DEV_OE pin

Hello everybody,

In the MAXII CPLD handbook there is mention made of a DEV_OE pin

which can be used to tristate the outputs of a CPLD for certain cases.

if this option is turned on, all outputs on the chip operate normally when dev_oe is asserted. when the pin is deasserted, all outputs are tri-stated.

However, what happens to the inputs in this situation ?

Thanks,

Eric

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    what happens to the inputs in this situation

    --- Quote End ---

    Obviously nothing.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    hello,

    I have a question about OE pins. For the max 7000s devices, it does talk about these global control signals for OE and the pins are there. However in quartus, the option for enabling OE is not there for these devices. After compilation, the report for fitter Fitter Device Options lists Enable device-wide output enable (DEV_OE) as off. Yet, I don't see where that setting can be changed. Does that option exist for that device family?

    Thanks.