Forum Discussion
GD76
Occasional Contributor
Occasional ContributorCPLD constraints
Where can I get information on locking all the macrocells through SDC file? The constraint editor document I have is talking about doing it through pin planner but like to do it through constraint SD...
Ganesan,
May I know if there is any update?
SyafieqS
Super Contributor
Super ContributorHi Ganesan,
I assume locking signal to microcell is probably feature like logic lock region and design partition in Quartus. You can preserve logic there are few method like logic lock, design partition post fit and back annotate. May refer to link below for details
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-optimization.pdf
- https://www.youtube.com/watch?v=XO0Qi_zIpPs
