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GD76's avatar
GD76
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

CPLD constraints

Where can I get information on locking all the macrocells through SDC file? The constraint editor document I have is talking about doing it through pin planner but like to do it through constraint SD...
  • SyafieqS's avatar
    SyafieqS
    4 years ago

    Ganesan,


    May I know if there is any update?


GD76's avatar
GD76
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

How to lock the routing of some signals to macrocells so build to build the routing does not change.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

The best method for doing this is to use a block-based design flow where you divide your design into design partitions and then "lock down" each partition as you complete its optimization. See the block-based design flow user guide:

https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html

If you're using Standard instead of Pro, look in the documentation for the "incremental compilation" feature.