CPLD clock skew generation

Thanks for the reply.

My code decodes address,data,,cs and r/w from a processor bus. The data is written and read to a fifo based on fifo_read and fifo_write. Since the clock for the processor bus signals is the same as the fifo clock I just wanted a few ns delay between fifo_read/write (generated by a state machine) to make sure the fifo_clock is stable before the fifo_read/write happens.

Without any phase difference between the closks the current design seems to give unpredictable read/writes results.