CPLD clock skew generation

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I use an epm2210 CPLD and need to generate two internal clocks of

50MHz with 3 to 8ns phase difference.

Any ideas?

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The MAX II devices do not have PLLs, so shifting the clock phase at 50MHz (20ns) is not going to be simple. You can invert the clock and get 10ns.

What are you trying to achieve? Perhaps there is an alternative.

Cheers,

Dave