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Altera_Forum
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15 years ago

CPLD clock issue

This might be a stupid question but I need to see where is the problem. I have two designs with an Altera CPLD MAX3000A, the difference between them is the clock input signal. Both clock signal...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks FvM, it's pretty clear for me now where things go wrong, but I still have one more question.

Is is possible to use that high rise/fall time signal as an input, clean the edges inside of CPLD and then use it as a main clock signal?