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Honored Contributor
Honored ContributorCPLD acting strangely
Hello. I designed an interface between an FPGA and a CPLD (MAXII) which is not entirely synchronous. The interface consists of 3 lines: Data, Clock and Enable. Each command transfered is 32 bits l...
Altera_ForumHonored Contributor
Honored ContributorDid you set the timing constraints including the delays from the input lines to the first registers?
Maybe these delays are very different and your design doesn't work since the input data are synchronized from the wrong input clock.
