Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCPLD acting strangely
Hello. I designed an interface between an FPGA and a CPLD (MAXII) which is not entirely synchronous. The interface consists of 3 lines: Data, Clock and Enable. Each command transfered is 32 bits l...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Is it possible that the timing simulation is not showing problems inside the CPLD, although they exist? --- Quote End --- Sounds like a design fault. It's not necessarily shown in timing simulation, because it hardly reproduces the exact input signal and device internal timing.
