Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorcounter VHDL
hi, i am trying to make a counter using the 50Mhz clock on my board DE1, when i LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY teller IS
PORT (
...
Altera_ForumHonored Contributor
Honored Contributorthe output2 looks like its half power because its flashing at 50MHz, with 50% on and 50% off time.
have you connected the clock to an actual clock pin?
