Is there anyway in Altera or Verilog code such that the counter gets reset to zero only on power ON. Please advise. (I am using EP2C35F672C6 "Cyclone II" within DE2 board)

what do you actually mean? Please give some more details.

Registers have a power on reset state, it can be defined e.g. as an initial value in VHDL signal definition.

--- Quote Start --- what do you actually mean? Please give some more details. --- Quote End --- A sample code will make me easier to explain: module myTest(clk,_reset,outcnt); input clk,_reset; output reg [7:0] outcnt; always @(posedge clk or negedge _reset) begin if(_reset==1'b0) outcnt<=8'h00; else outcnt<=out+1'b1; end endmodule Here, _reset is connected to external switch. So, anytime someone pushes that switch, outcnt becomes 8'h00. But, what I really want to happen is that I want outcnt be zero only at Power ON. (If I remove _reset signal, what will the initial value of the outcnt at Power ON?) Is there anyway I can work on DE2 board with Altera 2c35 or Quartus S/W to specify this? Thanks.

I'm not so familiar with Verilog, but Quartus should infer register power-up reset from Verilog initial block: initial begin outcnt<=8'h00; end There is also an power-up option for registers in assigment editor, but HDL assignment is more comfortable.

The register will have the power up condition as stated in the verilog design. I found some instructions on how it can be done different in the quartus help : // Use a variable declaration assignment to set the power-up level // of an inferred register. reg q = 1'b1; always@(posedge clk) begin q <= d; end So it was time to do some tests : - when a reset condition is specified in the verilog code like this : reg q; always@(posedge clk or posedge reset) begin if (reset) q <= 0; else q <= d; end Then the reset condition (q <= 0 ) is used as startup value, regardless the specified initial condition. Even if I set "reg q = 1", the value for the register is zero after configuration. - when you don't specify a reset condition in the always block, the initial condition specified is used. However I didn't found a way to visualize the reset condition in the quartus environment (also not in the chip editor). Stefaan

Counter Power on Reset only | Altera Community

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Altera_Forum
Honored Contributor
17 years ago
Cyclone II physical registers always power up to 0, and have ACLR support. When the designer requests either APRE or power up to 1 the software will emulate it with not-gate-push. To not-gate-push inverters are added before and after the register, and the APRE changes to an ACLR. This makes the register look like it powers up to 1 as viewed from surrounding logic. Mismatching power / reset states can be emulated with some extra logic, or implemented directly on some of the other chip families, but it's pretty unusual.

Quartus will recognize the "initial" described by FvM above. If there is no initial assignment to 1 or 0 the rule is actually "don't care" by default. It will show power up to "X" in modelsim, and Quartus may select a 1 if it can use the 1 to reduce the logic. Otherwise it sticks to the natural 0.

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Counter Power on Reset only

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