Counter Power on Reset only

Cyclone II physical registers always power up to 0, and have ACLR support. When the designer requests either APRE or power up to 1 the software will emulate it with not-gate-push. To not-gate-push inverters are added before and after the register, and the APRE changes to an ACLR. This makes the register look like it powers up to 1 as viewed from surrounding logic. Mismatching power / reset states can be emulated with some extra logic, or implemented directly on some of the other chip families, but it's pretty unusual.

Quartus will recognize the "initial" described by FvM above. If there is no initial assignment to 1 or 0 the rule is actually "don't care" by default. It will show power up to "X" in modelsim, and Quartus may select a 1 if it can use the 1 to reduce the logic. Otherwise it sticks to the natural 0.