Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCounter in VHDL
Hi, I want to design a 16 bit counter with 1uSec resulution. I have only 40MHz clock and can't use neither PLL or frequency divider. I can use only the 40MHz global clock. Can somebody reco...
Altera_ForumHonored Contributor
Honored Contributorrun another counter at 40MHz. When it reaches a given number generate an enable that increases the main 16 bit counter.
