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Altera_Forum
Honored Contributor
Honored ContributorCounter in VHDL
Hi,
I want to design a 16 bit counter with 1uSec resulution. I have only 40MHz clock and can't use neither PLL or frequency divider. I can use only the 40MHz global clock. Can somebody recommend for VHDL design for 16 bit counter with resulution adjustment? THX GUY.5 Replies
Altera_ForumYou will need 16+6 flops and some logic at the minimum.
- Altera_Forum
Thank you .
- Altera_Forum
Possibly.
If you come up with other ideas, give them a go too and look at resource usages. - Altera_Forum
Thank you!
I want to implement it in minimum hardware. You think this is the most minimized option? Guy. - Altera_Forum
run another counter at 40MHz. When it reaches a given number generate an enable that increases the main 16 bit counter.
