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Altera_Forum
Honored Contributor
Honored ContributorCounter Code Errors
LIBRARY ieee;
USE ieee.std_logic_1164.all; ENTITY CounterQ2 IS Port(clk, reset, up :IN STD_LOGIC; abc :INOUT BIT_VECTOR(2 downto 0); zero :OUT STD_LOGIC; full :OUT STD_LOGIC); END CounterQ2; ARCHITECTURE circuit OF CounterQ2 IS BEGIN PROCESS(clk, reset) BEGIN IF (reset = '1') THEN abc <= "000"; ELSIF RISING_EDGE(clk) THEN IF (up='1') THEN IF abc = "000" THEN abc <= "001"; ELSIF abc = "001" THEN abc <= "011"; ELSIf abc = "011" THEN abc <= "010"; ELSIF abc = "010" THEN abc <= "110"; ELSIF abc = "110" THEN abc <= "111"; ELSIf abc = "111" THEN abc <= "101"; ELSIF abc = "101" THEN abc <= "100"; ELSIF abc = "100" THEN abc <= "000"; END IF; END IF; IF (up = '0') THEN IF abc = "000" THEN abc <= "100"; ELSIF abc = "001" THEN abc <= "000"; ELSIF abc = "011" THEN abc <= "001"; ELSIF abc = "010" THEN abc <= "011"; ELSIF abc = "110" THEN abc <= "010"; ELSIF abc = "111" THEN abc <= "110"; ELSIF abc = "101" THEN abc <= "111"; ELSIF abc = "100" THEN abc <= "101"; END IF; END IF; END IF; IF abc = "000" THEN zero <= '1'; ELSIF abc /= "000" THEN zero <= '0'; END IF; IF abc = "100" THEN full <= '1'; ELSIF abc /= "100" THEN full <= '0'; END IF; END PROCESS; END circuit;2 Replies
Altera_Forum--- Quote Start --- you don't really need the "up" term in the sensitivity list --- Quote End --- The up = '0' condition is outside the clock sensitive block, thus you get a compiler warning, when you omit up from the sensitivity list, although the synthesized code is correct anyway. But it can cause different behaviour in simulation. Bracketing isn't required in VHDL except for controlling operator precedence. In the present code, you don't need it. --- Quote Start --- ELSE IF should be ELSIF --- Quote End --- Yes, that's the error cause in the code, as far as I see.- Altera_Forum
I think your last "end if" should be an "end process".
Also noticed in line PROCESS(clk, reset,up) you don't really need the "up" term in the sensitivity list for synchronous processes as you only want the process sensitive to the clock an reset. This may cause a difference between simulation and actual behavior. Line 45: IF up = ('0') THEN The bracketing is a bit odd.... Should be OK bit maybe IF (up = '0') THEN is more standard. Also ELSE IF should be ELSIF Hope this helps
