Counter Code Errors

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY CounterQ2 IS

Port(clk, reset, up :IN STD_LOGIC;

abc :INOUT BIT_VECTOR(2 downto 0);

zero :OUT STD_LOGIC;

full :OUT STD_LOGIC);

END CounterQ2;

ARCHITECTURE circuit OF CounterQ2 IS

BEGIN

PROCESS(clk, reset)

BEGIN

IF (reset = '1') THEN

abc <= "000";

ELSIF RISING_EDGE(clk) THEN

IF (up='1') THEN

IF abc = "000" THEN

abc <= "001";

ELSIF abc = "001" THEN

abc <= "011";

ELSIf abc = "011" THEN

abc <= "010";

ELSIF abc = "010" THEN

abc <= "110";

ELSIF abc = "110" THEN

abc <= "111";

ELSIf abc = "111" THEN

abc <= "101";

ELSIF abc = "101" THEN

abc <= "100";

ELSIF abc = "100" THEN

abc <= "000";

END IF;

END IF;

IF (up = '0') THEN

IF abc = "000" THEN

abc <= "100";

ELSIF abc = "001" THEN

abc <= "000";

ELSIF abc = "011" THEN

abc <= "001";

ELSIF abc = "010" THEN

abc <= "011";

ELSIF abc = "110" THEN

abc <= "010";

ELSIF abc = "111" THEN

abc <= "110";

ELSIF abc = "101" THEN

abc <= "111";

ELSIF abc = "100" THEN

abc <= "101";

END IF;

END IF;

END IF;

IF abc = "000" THEN

zero <= '1';

ELSIF abc /= "000" THEN

zero <= '0';

END IF;

IF abc = "100" THEN

full <= '1';

ELSIF abc /= "100" THEN

full <= '0';

END IF;

END PROCESS;

END circuit;