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Altera_Forum
Honored Contributor
Honored ContributorCounter Code Errors
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY CounterQ2 IS Port(clk, reset, up :IN STD_LOGIC; abc :INOUT BIT_VECTOR(2 downto 0); zero :OUT STD_LOGIC; full :OUT STD_LO...
Altera_ForumHonored Contributor
Honored ContributorI think your last "end if" should be an "end process".
Also noticed in line PROCESS(clk, reset,up) you don't really need the "up" term in the sensitivity list for synchronous processes as you only want the process sensitive to the clock an reset. This may cause a difference between simulation and actual behavior. Line 45: IF up = ('0') THEN The bracketing is a bit odd.... Should be OK bit maybe IF (up = '0') THEN is more standard. Also ELSE IF should be ELSIF Hope this helps
