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you don't really need the "up" term in the sensitivity list
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The up = '0' condition is
outside the clock sensitive block, thus you get a compiler warning, when you omit up from the sensitivity list, although the synthesized code is correct anyway. But it can cause different behaviour in simulation.
Bracketing isn't required in VHDL except for controlling operator precedence. In the present code, you don't need it.
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ELSE IF should be ELSIF
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Yes, that's the error cause in the code, as far as I see.
Honored Contributor
