Could not find rtl_work.TB.vhd

There is nothing you need to see, almost all files use:

Don't bother, I sent my project to your mail (only the skeleton, there is no code even knowing the skeleton shows much...).

As you can see it's an easy project don't remember this to me... if anyone has 2 months for a project...

As promised, here is an example of how to setup Quartus to synthesize against the fixed-point package compiled into the ieee_proposed library, i.e., the original library files are not modified.

VHDL fixed-point package synthesis example
------------------------------------------
9/13/2012 D. W. Hawkins ([email protected])
This design shows a minimal example that uses the
IEEE proposed fixed-point packages.
During synthesis, there will be warnings in the Quartus message
window about the design not meeting timing. This is to be expected,
as there is no .SDC file included in this example. This design is
not meant to be downloaded into a device, its merely to show how 
to setup Quartus to use the fixed-point package library.
To synthesise the design:
1) Start Quartus
2) Make the Tcl console visible using
   View->Utility Windows->Tcl console
   
3) Change directory to the location of this example code,
   eg., if the zip file was unzipped into 
   c:\temp\vhdl_fixed_pkg_example, then at the Tcl console type
   cd {C:\temp\vhdl_fixed_pkg_example}
   The paranthesis {} allow the Windows path separator '\'
   to be used in the name, otherwise you need to use '/', i.e.,
   
   cd C:/temp/vhdl_fixed_pkg_example
4) Then source the file
    source scripts/synth.tcl
    The Tcl script will output its progress:
    Synthesizing the 'fixed_pkg_example' design
    -------------------------------------------
     - Quartus Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
     - Creating the Quartus work directory
       * C:/temp/vhdl_fixed_pkg_example/qwork
     - Create the project 'fixed_pkg_example'
       * create a new fixed_pkg_example project
     - Creating the VHDL files list
     - Applying constraints
     - Processing the design
     - Processing completed
   The synth.tcl script has configured a Quartus project. After this
   point, you can edit files (eg. change parameters in fixed_pkg_example)
   and press play on the GUI to re-synthesize the design.
   
5) In the Quartus GUI, on the left-side is the "Project Navigator"
   window. The "Hierarchy" tab will be selected.
   
a) The "Hierarchy" window has a slider bar along the bottom.
   Slide it and you will see that this simple design requires
   a single DSP Block in the Cyclone IV E device.
b) Click on the "Files" tab. There will be four files listed:
   
   fixed_float_types_c.vhd
   fixed_pkg_c.vhd
   sfixed_multiply.vhd
   fixed_pkg_example.vhd
   
   These files are listed in the order they are compiled. The
   packages need to be compiled before any files that use them.
   
   Select the fixed_float_types_c.vhd file, right-click, and
   select "Properties". Note that the "Library" field is
   ieee_proposed. This is the VHDL library that the 
   fixed_pkg_c.vhd code expects to find type definitions,
   i.e., at the top of the file fixed_pkg_c.vhd is the lines
   
   library IEEE_PROPOSED;
   use IEEE_PROPOSED.fixed_float_types.all;

Hello,

Hi Alfonso,