Hello, The same process is giving issues once again: # ** Error: (vsim-3170) Could not find 'C:\Users\Alfonso\Desktop\PFC\simulation\modelsim\ rtl_work.TB_PFC_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34 I remember to delete the work folder to be able to compile a library that need that according to a modelsim tutorial: http://doc.union.edu/118/se_tutor.pdf (http://doc.union.edu/118/se_tutor.pdf) I have to do vcom <vhdl files .vhd> # do this for all the files cause it had to be done in the work folder, this may have caused the issue. i'm lost, can anyone help me?.

--- Quote Start --- Please, can anyone help me? --- Quote End --- The VHDL code is trying to use a component compiled into the rtl_work library. You can either compile your code into rtl_work via; vsim> vlib rtl_work vsim> vmap rtl_work [pwd]/rtl_work vsim> vcom -work rtl_work <your VHDL files> or you can simply map the rtl_work library to the same location as the work directory, eg., assuming you have created your work directory in the same folder you are working in via vsim> vlib work vsim> vmap work [pwd]/work then you can tell Modelsim to look in the work directory for the rtl_work components too by mapping it via vsim> vmap rtl_work [pwd]/work (You don't need the [pwd] statement if you don't want to use absolute paths in your .ini or .mpf file). Cheers, Dave

--- Quote Start --- The VHDL code is trying to use a component compiled into the rtl_work library. You can either compile your code into rtl_work via; vsim> vlib rtl_work vsim> vmap rtl_work [pwd]/rtl_work vsim> vcom -work rtl_work <your VHDL files> --- Quote End --- Hello, by typing this, how do you fill <your vhdl files>, by typing my vhdl files root (C:\Users\Alfonso\Desktop\PFC\altera) returns this: (I typed vsim> vcom -work rtl_work C:\Users\Alfonso\Desktop\PFC\altera) # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# ** Error: (vcom-7) Failed to open design unit file "C:UsersAlfonsoDesktopPFCltera" in read mode.# Invalid argument. (errno = EINVAL)# E:/altera/11.1sp2/modelsim_ase/win32aloem/vcom failed. --- Quote Start --- or you can simply map the rtl_work library to the same location as the work directory, eg., assuming you have created your work directory in the same folder you are working in via vsim> vlib work vsim> vmap work [pwd]/work then you can tell Modelsim to look in the work directory for the rtl_work components too by mapping it via vsim> vmap rtl_work [pwd]/work (You don't need the [pwd] statement if you don't want to use absolute paths in your .ini or .mpf file). Cheers, Dave --- Quote End --- It did not work, assuming [pwd] is written as [pwd] litterally (if it is a root instead, tell me) after typing those three lines literally as you did it continues returning me: # ** Error: (vsim-3170) Could not find 'C:\Users\Alfonso\Desktop\PFC\simulation\modelsim\rtl_work.TB_PFC_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34 Please help me i cannot test my code till this is solved.

--- Quote Start --- by typing this, how do you fill <your vhdl files>, by typing my vhdl files root (C:\Users\Alfonso\Desktop\PFC\altera) returns this: (I typed vsim> vcom -work rtl_work C:\Users\Alfonso\Desktop\PFC\altera) --- Quote End --- You've passed it a directory, not a VHDL file. You need to pass the vcom command the files that end in .vhd. You need to compile all of your files into the work library. If you are using Modelsim-ASE, then you do not need to compile Altera libraries. Cheers, Dave

Thank you for the effort. I typed: ... vcom -work rtl_work fixed_float_types_c.vhdl and it returned: # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# ** Error: (vcom-7) Failed to open design unit file "fixed_float_types_c.vhdl" in read mode.# No such file or directory. (errno = ENOENT)# E:/altera/11.1sp2/modelsim_ase/win32aloem/vcom failed. I moved from desktop to D: and tried again but failed with the same code, i try giving them write licence to all project files and folders, also with that failed. Alfonso.

Could not find rtl_work.TB.vhd | Altera Community

80 Replies

Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Again, i don't know what a Tcl script is

--- Quote End ---

Then you are not "listening" to what I am trying to explain to you. A Tcl script is just a series of commands.

You are using a Tcl script called PFC.tcl - where did it come from?

--- Quote Start ---

"You must also run the Tcl from the Quartus console. You do that by sourcing the file" This (if it is the Tcl script) returns nothing

--- Quote End ---

The Tcl script will do whatever you have written in it. If you have not written it to print messages, then of course it will not display anything in the console.

--- Quote Start ---

Yes i'm a useless engineer, but i'm trying to end my degree.
--- Quote End ---

Don't take it that way. You are an "inexperienced" engineer. However, if you expect anyone to help you now and in the future, when you ask for advice, you need to listen to it, and then formulate follow-on questions indicating what you have done, and what you have failed to understand.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Then you are not "listening" to what I am trying to explain to you. A Tcl script is just a series of commands.

You are using a Tcl script called PFC.tcl - where did it come from?

--- Quote End ---

I suppose was generated from files, if U go on on asking existence questions about tcl, then maybe i should ask for a better bibliography...

--- Quote Start ---

The Tcl script will do whatever you have written in it. If you have not written it to print messages, then of course it will not display anything in the console.

--- Quote End ---

Okay, what do this answer got to do with the modelsim compiling succesfull?

--- Quote Start ---

Don't take it that way. You are an "inexperienced" engineer. However, if you expect anyone to help you now and in the future, when you ask for advice, you need to listen to it, and then formulate follow-on questions indicating what you have done, and what you have failed to understand.

Cheers,
Dave
--- Quote End ---

Don't blame why young people don't study nowadays, sometimes i understand them, to get shattered this way.
Altera_Forum
Honored Contributor
13 years ago
To resume, after the prodigious sourcing of the code, this is the situation.

error (10481): vhdl use clause error at producten.vhd(3): design library "work" does not contain primary unit "fixed_package"
error (10800): vhdl error at producten.vhd(3): selected name in use clause is not an expanded name
error: quartus ii 32-bit analysis & synthesis was unsuccessful. 2 errors, 1 warning
Altera_Forum
Honored Contributor
13 years ago
Please if you are not gonna go directly to the whole mess, please connect more continously, or focus more.
Altera_Forum
Honored Contributor
13 years ago
Well, like you don't realise my situation and don't bother tell me a bad stdent, i will tell you that i cannot do the researching figure you would expect because i've got 10 days to endy my project if i fail, i will have to repeat the subject again, do you understand my hurries? Hope so.

And i've spent 3 days wandering without any advance, how do you think i would feel?
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
don't bother tell me a bad stdent
--- Quote End ---

I'm not telling you you are a bad student. I am giving you advice on how to learn, regardless of whether you are a student or not.

Keep in mind that I do not work for Altera and do not have to help you. No one on this forum does. If you want help, then you have to have a good attitude in return.

I understand you are frustrated. The tools are complicated. You should have been given more time than 10 days to learn how to use a tool and to complete a project.

I can see that you are overwhelmed. Why don't you post your code and let me take a look. I'll try and setup a Quartus project for you that will work.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
I'm not telling you you are a bad student. I am giving you advice on how to learn, regardless of whether you are a student or not.

Keep in mind that I do not work for Altera and do not have to help you. No one on this forum does. If you want help, then you have to have a good attitude in return.

I understand you are frustrated. The tools are complicated. You should have been given more time than 10 days to learn how to use a tool and to complete a project.

I can see that you are overwhelmed. Why don't you post your code and let me take a look. I'll try and setup a Quartus project for you that will work.

Cheers,
Dave
--- Quote End ---

Well,

1 I've been given a year, but the subject that teach me VHDL started on february.
2 The final exercise of the subject was to use I2C to start a D2 audio, i did never see I2C until this year, as a result to my poor skills, and thankfully i was helped by a colleage, i finished the 20 of july, on 30 of july my teacher who holds my project, went on holidays 30 days so he explained poorly my project by ovius reasons, so i didn't started (In summer i made the memory and all the teoric research) since 1 september, it has taken 12 days to wrote all codes in those 10 files you could see, nowadays i'm stuck in the modelsim that during the exercise didn't gave me any problems, i've asked my exercise master of the university and doesn't have any clue of Modelsim. So here we are.

Please help me as fast as you can, i go to a privete school since i am no good student for a public one and a single subjects costs lots of money to repeat it cause modelsim does not work.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---

it has taken 12 days to wrote all codes in those 10 files you could see

--- Quote End ---

Please upload a zip file with the files, and I'll take a look.

--- Quote Start ---

Please help me as fast as you can
--- Quote End ---

Ok.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
I should not post my code is my final 5th year engineering project by obvius reasons i can't.

Yes it is an easy project but i did not have more time for something bigger.
Altera_Forum
Honored Contributor
13 years ago
They can blame me on copiing if somebody advances me.

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Could not find rtl_work.TB.vhd

80 Replies

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