Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCould a dual clock dual input DFF be implemented in FPGA?
Could a dual clock dual input DFF be implemented in FPGA? What I need is : process (clk1,clk2) begin if ( (clk1'event) and (clk1 ='1')) then dout<=din1; end if;...
Altera_ForumHonored Contributor
Honored ContributorIf there is no overlapping of the clocks and they are of the same freq, this is nothing than a set-reset behaviour. You can setup a toggle FF for each of the clocks and add the output. Thus the ouput becomes odd after the first clock and even after the second clock rise. Bit 0 of this adder is the selector for the MUX
