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Altera_Forum
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18 years ago

Could a dual clock dual input DFF be implemented in FPGA?

Could a dual clock dual input DFF be implemented in FPGA? What I need is : process (clk1,clk2) begin if ( (clk1'event) and (clk1 ='1')) then dout<=din1; end if;...
Altera_Forum's avatar
Altera_Forum
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18 years ago

The maximum distance between the rising edges of clk1 and clk2 is 1us.

Yes,both clk1 and clk2 is 50% duty cycle.

In fact ,clk1 and clk2 is the output of the same pll, with the same frequncy and differrent phases. The phase distance could be progammed.( range 10ns to 1us).