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Honored Contributor
Honored ContributorCould a dual clock dual input DFF be implemented in FPGA?
Could a dual clock dual input DFF be implemented in FPGA? What I need is : process (clk1,clk2) begin if ( (clk1'event) and (clk1 ='1')) then dout<=din1; end if;...
Altera_ForumHonored Contributor
Honored ContributorPhysically, there is no such thing as a two-edge register. Do you know the maximum distance between the rising edges of clk1 and clk2? Are the duty cycles 50/50? You might be able to build a mux that chooses which clock drives the register(this is a tricky thing to do, so don't tread lightly), but would require a known relationship between the clocks.
Or, maybe have two registers grabbing the data separately, and then muxing between their outputs?
