Could a dual clock dual input DFF be implemented in FPGA?

Physically, there is no such thing as a two-edge register. Do you know the maximum distance between the rising edges of clk1 and clk2? Are the duty cycles 50/50? You might be able to build a mux that chooses which clock drives the register(this is a tricky thing to do, so don't tread lightly), but would require a known relationship between the clocks.