Forum Discussion
5 Replies
- Altera_Forum
Honored Contributor
You can find that out easily by creating and compiling a simple verilog or vhdl with the circuit you are interested in. Quartus produces comprehensive reports of resource usage on a particular FPGA family when you compile.
- Altera_Forum
Honored Contributor
--- Quote Start --- You can find that out easily by creating and compiling a simple verilog or vhdl with the circuit you are interested in. Quartus produces comprehensive reports of resource usage on a particular FPGA family when you compile. --- Quote End --- Thank you Galfonz for your answer, effectively, we can have the cost of implementation of circuits using the report provides in quartus, but i want the cost of basic arithmetic and logical operators before starting the coding because I want to use these settings elsewhere. I searched into the datasheet of altera but I only found one example of the multiplier 19*19 bits - Altera_Forum
Honored Contributor
I should have mentioned specifically in my reply that I don't know of any such documentation. I don't know if a given operation will always take the same resources. It might depend on the context and on what timing constraints you've entered. I know I've seen resource usage change significantly by what look like small changes to code and/or timing constraints.
- Altera_Forum
Honored Contributor
There is no such data available, because the synthesisor can do lots of work to minimise logic usage depending on your design. Also, the device family has a large effect on resource usage depending on whether it uses 4/6 input LUTs.
So there is no such thing as logic usage for a basic block. - Altera_Forum
Honored Contributor
Hi,
Yah I agree to Galfonz. The best way to figure this out is to write a sample code and synthesize it. Because the number of logic elements will differ for different devices and timing constraints. Thanks,