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Altera_Forum
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15 years ago

Cosine and Sine lookup table in vhdl

Hi i'm new to vhdl and I need a cosine and sine lookup table file in vhdl file already DONE.. because I don't have much time.. please help! thanks.

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  • Altera_Forum's avatar
    Altera_Forum
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    Have this: A license file is required to enable compilation of your design for the Stratix II family devices. Visit Altera Licensing.... :(

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    Altera_Forum
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    Hi,

    I am new to FPGA and want to generate the sine wave. I read your threads and can you please tell me that i have to interface this sincos_lut.vhd file to DAC directly or i have to write some intermediate module?
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    Altera_Forum
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    If you want to generate the terms in sequence look up the Goertzel generator, one multiple and an add per term (from the previous 2):

    sin(a+b) = 2sin(a)cos(b) - sin(a-b)
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Attached a direct LUT in vhdl

    The input theta_in is the address, you can increment it as you wish to skip samples e.g. increment by 1 to use full table or by 2 to use half table or by 4 to use quarter table and so on.

    --- Quote End ---

    :D Helo!!! could you tell me, how to use this table?? the input theta is in dreegres?? and, how I have to interpret the outputs.

    thanks
  • Altera_Forum's avatar
    Altera_Forum
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    The input is 12 bits counter (not degrees but represents phase) and usually you start from zero and increment by tuning word(tw) as below. The LUT size is 4096 locations. data is 12 bits wise signed.

    To produce a given frequency, you first need to know your sampling rate (Fs)

    then your required output frequency (Fo) then compute a tuning word:

    the ratio of tw/lut size = Fo/Fs i.e.

    tw = lut size * Fo/Fs = 4096 *Fo/Fs -- rounded up

    The lowest frequency is when tw = 1 and the highest frequency is when tw = 2048 i.e. the phase jumps 0 => 2048 => 0

    You need to increment phase by tw modulo 4096.

    Hope this helps