Altera_Forum
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Honored ContributorCosine and Sine lookup table in vhdl
Hi i'm new to vhdl and I need a cosine and sine lookup table file in vhdl file already DONE.. because I don't have much time.. please help! thanks.
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Altera_Forum--- Quote Start --- It's your decision where to place it. Obviously the DAC data representation isn't signed. --- Quote End --- Totally true. Solved about an hour after asking here :) 95Hz sine, 1k+0.1uF RC filter on output: http://i.imgur.com/CvoI4.jpg- Altera_Forum
Hi, How did u manage to solve it and got that sine wave.
- Altera_Forum
The LUTs are signed 2's complement. If your DAC device that reads these LUTs isn't signed 2's complement then you need to match the number system. Possibly your DAC might be offset binary which is different from 2's complement as follows:
The sign and magnitude is not much in use as it makes signed multiplication weird relative to 2sc which makes it similar to unsigned. offset is favoured by some DAC/ADC vendors as it makes their design easier since there is natural binary transitio of negative numbers just like positive numbers. The designer needs just to invert the sign bit to convert between offst and 2sc. notice it is the interpretation of binary strings that differs e.g. when DAC looks at 1011 string then it uses it to mean -5 if it uses 2'sc or +3 if it uses offset or -3 if it uses s&m or 11 if it uses unsigned. Hence given binary string 1011 in offset system (+3) then it should map to +3 of 2'sc list i.e. 0011 thus just needs sign bit inversion.binary 2'sc offset sign&mag unsigned 0000 0 -8 0 0 0001 +1 -7 +1 1 0010 +2 -6 +2 2 0011 +3 -5 +3 3 0100 +4 -4 +4 4 0101 +5 -3 +5 5 0110 +6 -2 +6 6 0111 +7 -1 +7 7 1000 -8 0 0 8 1001 -7 +1 -1 9 1010 -6 +2 -2 10 1011 -5 +3 -3 11 1100 -4 +4 -4 12 1101 -3 +5 -5 13 1110 -2 +6 -6 14 1111 -1 +7 -7 15 - Altera_Forum
Thanks for that Kaz .... i fixed this problem by giving a "011111111111" offset.........
- Altera_Forum
The implementation was, in FPGA? and you used NCO megacore function of Altera?
- Altera_Forum
FPGA + external DAC
- Altera_Forum--- Quote Start --- FPGA + external DAC[/QUOTE May you Share the project of Quartus, Im try to create this LUT with Cyclone III but my level of vhdl is basic, your project can answer to my cuestions is only for academic purpose. I apreciate your colaboration. :o excuse me for my bad english!
- Altera_Forum
Unfortunately that one was made using Spartan-3E and as You can see - a year ago. I've moved to Altera since then :)
- Altera_Forum--- Quote Start --- Unfortunately that one was made using Spartan-3E and as You can see - a year ago. I've moved to Altera since then :) --- Quote End --- But don't have any document with specifications or algorithms, documentation ? Or you have the project of Xilinx ISE, can i open this and verify! :)
- Altera_Forum
