Honored Contributor
Honored ContributorHi,
My evaluation board has cfi flash(8 MB) and my aim is to program both Hardware and Software file permanently on FPGA. I took the reference of https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04112006_450.html and http://www.alterawiki.com/wiki/flash_programmer#1._sof_in_epcs.2c_program_in_cfi and I tried following steps: 1. sof2flash --epcs --input=SBC_OTDR.sof --output=flash1.flash --verbose 2. elf2flash --base=0x01800000 --end=0x01ffffff --reset=0x01800000 --input=stack.elf --output=flash2.flash --boot=boot_loader_cfi.srec where 0x01800000 and 0x01ffffff are the base and end address of cfi flash and 0x01800000 (i.e. cfi flash) is reset address of Niosii in my Qsys and I copied boot_loader_cfi.srec file directly working folder instead of giving path. I have configured in Qsys cfi flash by means of Generic Tristate controller, Tri-State conduit pin sharer and Tri-state conduit bridge instantiate them accordingly in verilog design file. 3. nios2-elf-objcopy --input-target srec --output-target ihex flash2.flash hex1.hex 4. Then I used Quartus to convert .sof and .hex file to .pof and load it onto EPCS64 in active serial mode. But unfortunately software part didn't work. But they work separately in .sof and .elf form error free. What I am missing here? or my approach is wrong? P.S. I once confused whether I have cfi or EPCS flash but user manual of my board don't have 4 pins(data0, dclk, sce, sdo) required for EPCS as mentioned in this tutorial. http://www6.in.tum.de/pub/main/teachingws2013mse/tutorial.pdf
