Converting .sof and .elf to make single .pof

Hi,

in the meantime, I could manage to buy the licence and now using full version .sof file (not time limited version) but still I have the same problem.

Any suggestion.

or there is another way to permanently program FPGA with .pof and .elf file?

There is not any way to do this from within Quartus.

The first thing to fix would be nios2-elf-objcopy not producing any output .hex file. If your post is accurate, it looks like you're not invoking the command properly? Here is the command I use from my scripts:

nios2-elf-objcopy --input-target srec --output-target ihex ${ELFFILE}.srec ${HEXFILE}

i.e. GNU-style double-dash "--" argument prefixes.

Hi,

Thanks, now I can generate .hex file.

But the problem now is when I use Convert Programming file function of Quartus II to combine this .hex with .sof to generate single .pof file and load it on FPGA in active serial mode. The hardware part(.sof) working/load correctly but not the software part(.elf/.hex).

while converting I chose start address for .sof at 0x0 and for .hex Relative addressing 0x00367F06 (While converting alone .sof file to .pof I found in .map file start address 0x0 and end address 0x00367F05. Therefore I chose just after that).

But When I run that elf file separately by niosii command mode:

nios2-download -g filename.elf

it works correctly and come info as:

"starting processor at address 0x080001BC"

which is actually the SDRAM address(Base: 0x08000000 End: 0x0fffffff) which I used in my Qsys.

but when I use this address as relative address for hex file while converting to single .pof,

It shows memory exceeds even after compression of .sof file.

Does It have also to do with EPCS128/EPCS64, which I mentioned in post# 1.

What could be the reason?

Any suggestion please.

The method that you are attempting to use will end up with the FPGA configuration data at the beginning of the EPCS, and the NIOS firmware sitting in EPCS right after that.

The NIOS firmware is not directly usable when it is sitting in the EPCS flash. It needs to be copied from EPCS to RAM before the NIOS starts executing.

This relocation is usually performed by the boot loader included with the "EPCS Serial Flash Controller" IP block. So if you haven't already, you need to add that core and configure it appropriately, and have your NIOS reset vector point to it.

If you search around for "NIOS EPCS boot" there's many other threads/appnotes/knowledgebase related to it.

Hi,

My evaluation board has cfi flash(8 MB) and my aim is to program both Hardware and Software file permanently on FPGA.

I took the reference of

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04112006_450.html

and

http://www.alterawiki.com/wiki/flash_programmer#1._sof_in_epcs.2c_program_in_cfi

and I tried following steps:

1. sof2flash --epcs --input=SBC_OTDR.sof --output=flash1.flash --verbose

2. elf2flash --base=0x01800000 --end=0x01ffffff --reset=0x01800000 --input=stack.elf --output=flash2.flash --boot=boot_loader_cfi.srec

where 0x01800000 and 0x01ffffff are the base and end address of cfi flash and 0x01800000 (i.e. cfi flash) is reset address of Niosii in my Qsys and I copied boot_loader_cfi.srec file directly working folder instead of giving path. I have configured in Qsys cfi flash by means of Generic Tristate controller, Tri-State conduit pin sharer and Tri-state conduit bridge instantiate them accordingly in verilog design file.

3. nios2-elf-objcopy --input-target srec --output-target ihex flash2.flash hex1.hex

4. Then I used Quartus to convert .sof and .hex file to .pof and load it onto EPCS64 in active serial mode.

But unfortunately software part didn't work.

But they work separately in .sof and .elf form error free.

What I am missing here? or my approach is wrong?

P.S. I once confused whether I have cfi or EPCS flash but user manual of my board don't have 4 pins(data0, dclk, sce, sdo) required for EPCS as mentioned in this tutorial.

http://www6.in.tum.de/pub/main/teachingws2013mse/tutorial.pdf

You can safely ignore the EPCS128 message, some Quartus command line tools write this when using EPCS, even when using a different size.

As ted suggested, check the NIOS configuration in QSys. Its reset vector should be set to the EPCS controller so that the CPU tries to load the elf file from the EPCS flash at boot up.

EDIT: this suggestion was only if you had both the FPGA design and the software in the EPCS. But as you say you are putting the software into a CFI flash, this doesn't apply. Please read my next message instead.