Converting Shift registers to memory

Hi

I am trying work with Shift registers and want them to be implemented with the STRATIX memory

How can I do that ? and how can I check in the Quartus reports that it was done.

When I create the S.R. it takes not to meny LCs but when I try to connect the S.R. last stage somewhere

the LC usage becomes too big to fit the device, why is that?

(* ramstyle = "M4K" *) reg [2677:0] RefBuff[15:0];

(* ramstyle = "M4K" *) reg [2677:0] InLine[15:0]; //S.R. for the incoming data

(* syn_ramstyle = "M4K" *) reg [2677:0] Line_Buff[15:0];

//################ InData to Shift Reg# #########################

always@(posedge Rx_clk_A)

begin

InLine[0] <= l[15:0];

end

always@(negedge Rx_clk_A)

begin

if ( write_port_A )

begin

for (I=0 ; I<15 ; I=I+1)

begin

InLine[I+1] <= InLine[I];

end

end

end