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Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- My question is how to create a project made in vhdl code in a block schematic representation......it can't be made by do create/udate->create ymbol files for current fle? --- Quote End --- Hi, as Daixiwen mentioned it is not possible to convert a project written in VHDL into a schematic. Why do you want a schematic ? Only to get an overview of the struture of your design? As Daixiwen mentioned you can use the RTL viever of Quartus for that purpose. Kind regards GPK