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Altera_Forum
Honored Contributor
16 years agoIt can't be done in that direction. If you want a graphical view of VHDL code, you can use the RTL viewer after synthesis. But it's not always easy to read
It can't be done in that direction. If you want a graphical view of VHDL code, you can use the RTL viewer after synthesis. But it's not always easy to read