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Altera_Forum
Honored Contributor
15 years agoConversion uses all combinational logic
Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum
Honored Contributor
15 years agoTricky, thank you very much for all your help. I'm a student and I mostly do software.
Could I implement a multiplier as follows, and if I did would this only instantiate a single multiplier that I could use over and over via a state machine. So in state A, I input the operands, then in state B, I receive the processes output?process(a,b,clk)
begin
if clk'event and clk='1' then
d<=a*b;
c<=d;
end if;
end process;