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Altera_Forum
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15 years ago

Conversion uses all combinational logic

Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

As a quick note to your very very slow design - I compiled it for a stratix 4 - and timequest said the max clock speed for your design would be 1.5MHz. On a Cyclone 2 it would be much slower.

So you need to sort out your design with decent pipelining.