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Altera_Forum's avatar
Altera_Forum
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15 years ago

Conversion uses all combinational logic

Hi, I'm having trouble converting from an integer to an 8 bit std_logic_vector. It complies and gives an error that all my combinational logic nodes are used. I'm using a cyclone II FPGA chip. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Looks like you're trying translate a C file - you even called your file main.vhd.

Id say go back to the drawing board. Think about what logic you're trying to implement and draw it out by hand before even touching a keyboard to type in any VHDL code.