conversion of std_logic (NOT std_logic_vector) to integer

A quite workable solution is to use a

std_logic_vector(0 downto 0)

as intermediate.

This saves you the annoying "if (bit_x='1') then ...; else ...; endif;"

Example:

variable i: integer;

variable a_bit : std_logic;

variable a_bitx : std_logic_vector(0 downto 0);

variable s: line;

..

-- integer to bit:

i := 1;

a_bitx <= std_logic_vector(to_unsigned(i,1);

a_bit <= a_bitx(0);

-- long alternative: if i=1 then a_bit <= '1'; else a_bit <='0'; endif;

-- and bit to e.g. text:

write(s, to_integer(unsigned(a_bitx)));

-- long alternative: if a_bit = '1' then write(s, string'("1")); else write(s, string'("0")); endif;

NOTE: Often, in a testbench, the std_logic a_bit is not needed anymore if you use a_bitx(0) instead