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Honored ContributorConversion from output to input base of VHDL module
Hey,everybody.
I am constructing an VHDL code for clock divider and specification of 2 pins. I need to trigger 2 pins using DE2 board for 1 clock cycle(auto trigger down itself after 1 clock cycle). However, i have no idea how to convert that output of my clock divider for the clock of my pin specification. Can anyone please help me? My clock divider convert 27MHz to 500KHz and i need to trigger these 2 pins(buttons from DE2 board) using 500kHz. My code for the pin specification are: process(clkin) --- i think my problem is here!!! begin if A0 = '1' and (rising_edge(clkin)) then A0_out <= '1'; count1 := '1'; if count1='1' and (rising_edge(clkin)) then A0_out<= '0'; count1 := '0'; end if; end if; end process; process(clkin) begin if convst = '1' and (rising_edge(clkin)) then convst_out <= '1'; count2 := '1'; if count2='1' and (rising_edge(clkin)) then convst_out<= '0'; count2 := '0'; end if; end if; end process;1 Reply
Altera_ForumHello,
Me, I am used to have a copy of the output signal in these cases.
Jérômearchitecture ... signal A0_out_s : std_logic; begin A0_out <= A0_out_s; process(clkin) begin if rising_edge(clkin) then if A0_out_s = '1' then A0_out_s <= '0'; elsif A0 = '1' then A0_out_s <= '1'; end if; end if; end process; end architecture...;
