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Altera_Forum
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16 years ago

Conversion from output to input base of VHDL module

Hey,everybody. I am constructing an VHDL code for clock divider and specification of 2 pins. I need to trigger 2 pins using DE2 board for 1 clock cycle(auto trigger down itself after 1 clock cyc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello,

Me, I am used to have a copy of the output signal in these cases. 


architecture ...
signal A0_out_s : std_logic;
begin
A0_out <= A0_out_s;
process(clkin)
begin
    if rising_edge(clkin) then        
        if A0_out_s = '1' then
             A0_out_s <= '0';
        elsif A0 = '1' then
             A0_out_s <= '1';
        end if;
    end if;
end process;
end architecture...;
Jérôme