Thank you Farabi,
I have identified that the Cyclone V SoC FPGA includes an HPS with two UART interfaces. This allows me to physically connect UART0 to the PC application and UART1 to the MCU, so the hardware connectivity aspect is clear.
The remaining question is about the internal operation of the HPS during firmware transfer. Specifically:
Do I need to develop custom software to manage data movement between UART0 and UART1 (e.g., by configuring registers, memory buffers, and flow control)?
Or does the HPS provide a built-in mechanism to automatically handle this, essentially functioning as a UART-to-UART bridge without additional intervention?
Oh by the way I have decided to use STM for MCU as you have suggested